RISC-V SoC with custom accelerators
Why
Some jobs are slow in software on a small chip: searching for a GPS satellite signal, or running a neural network next to a sensor. The point of a system-on-chip is to put a dedicated block next to the processor for exactly those jobs, and to prove the whole thing still works.
How
I designed a RISC-V processor with a memory-mapped bus and two accelerators on it: one that searches for GPS signals and one that runs a small neural network shrunk to eight-bit numbers. The processor hands the job to the block and reads back the answer. Every instruction it runs is checked against an independent reference model, and the design was taken through synthesis, with a low-power change proven equivalent to the original rather than just re-tested.
What came out
The network went from 139,813 cycles to 4,241 on the accelerator for a 0.03 percentage-point accuracy cost, and the GPS search ran 5.63 times faster than in software.
What broke
Two bugs the reference model caught that reading the code did not: an arithmetic shift that silently behaved like a logical one because of how Verilog propagates signedness, and a GPS search that reported its peak one chip late because an enable was registered instead of combinational. An early synthesis table also reported the wrong cell count, because it was read before technology mapping. All three are in the README.